Packet Scheduling in Next-Generation Multiterabit Networks

T he infrastructure required to govern Internet traffic volume, which doubles every six months, consists of two complementary elements: fast point-to-point links and high-capacity switches and routers. Dense wavelength division mul-tiplexing (DWDM) technology, which permits transmission of several wavelengths over the same optical media, will enable optical point-to-point links to achieve an estimated 10 terabits per second by 2008. However, the rapid growth of Internet traffic coupled with the availability of fast optical links threatens to cause a bottleneck at the switches and routers. Switches and routers consist of line cards and a switch fabric. A network processor that interfaces to the physical data links, decodes incoming traffic, and applies traffic shaping, filtering, and other policy functions resides on each line card, which is associated with a port. Actual data transmission across ports occurs on the switch fabric, which includes a crosspoint, a scheduler, and buffers. The crosspoint is a configurable interconnecting element that dynamically establishes links between input and output ports. The scheduler configures the crosspoint, allows buffered data to traverse , and repeatedly reconfigures the crosspoint for successive transmissions. A major debate exists on whether next-generation multiterabit routing scenarios should use optical or electrical switch fabrics. At first glance, all-optical switches are the straightforward solution because they enable high-speed multiterabit aggre-gation and concentration. However, emerging router functions, such as quality of service (QoS) provisioning, require that packets be buffered—typically at the network processors—until the scheduler grants transmission. Because dynamic optical buffering is impractical, delayed transmissions currently dictate using opto-electric and electro-optical conversions. Switching nodes, which entail simplified buffer and transmission management , more efficiently process network protocols deploying fixed packet sizes such as asynchronous transfer mode (ATM). The network processor typically segments variable-length packets, such as IP packets, into smaller, fixed-size data units that traverse the switch core and later reassembles them at the output ports for transmittal in their original format. The length of data units passing through the switch core directly affects switch architecture and performance. Larger data units relax the timing requirements imposed on the switching and scheduling mechanisms, while smaller-sized units offer finer switching granularity. Designs commonly use 64-byte data units as a trade-off. Accompanying the rapid pace of Internet traffic is the increasing popularity of multimedia applications sensitive to mean packet delay and jitter. To provide differentiated services, developers categorize incoming packets into QoS classes. For each QoS class, the router must not …